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IPC/JEDEC J-STD-609B April 2016 Supersedes: IPC/JEDEC J-STD-609A.01-2011 February 2011
JOINT INDUSTRY STANDARD Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly
Notice
IPC and JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of IPC or JEDEC from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than IPC or JEDEC members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by IPC or JEDEC without regard to whether their adoption may involve patents on articles, materials, or processes. By such action, IPC or JEDEC do not assume any liability to any patent owner, nor do they assume any obligation whatever to parties adopting the Recommended Standard or Publication. Users are also wholly responsible for protecting themselves against all claims of liabilities for patent infringement. The material in this joint standard was developed by the IPC Marking, Symbols and Labels for Identification of Assemblies, Components and Devices Task Group (4-34b) of the Materials Identification Subcommittee (4-34) and JEDEC Committee JC14.4 Quality Processes and Methods. Methods .
Please use the Standard Improvement Form shown at the end of this document.
For Technical Information Contact:
JEDEC Solid State Technology Association 3103 North 10th Street, Suite 240-S Arlington, VA 22201-2107 Tel 703 907.0026 Fax 703.907.7501 .
IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847.615.7105
©Copyright 2016. JEDEC Solid State Technology Association, Arlington, Virginia, and IPC, Bannockburn, Illinois, USA. All rights reserved under both international and Pan-American copyright conventions. Any conventions. Any copying, scanning or other reproduction of these these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States.
IPC/JEDEC Joint Standard J-STD-609B
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly Contents 1 1.1
Scope .......................... ........................... .............1 Purpose ................................................................1
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Reference Documents ........................... ..........................2 IPC........................ ........................... .................2 JEDEC .......................... ........................... .............2 IEC........................ ........................... .................2 European Parliament ......................................................2 ANSI ........................... ........................... .............3 GEIA ...................................................................3 European Standards ......................... .......................... ....3
3
Terms and Definitions ....................................................3
4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.3.1 4.3.2
Symbols, Labels, and Marks .......................... ......................5 Material Category Symbol ..................................................5 Size and Location .........................................................5 Color ...............................................................5 Font ...............................................................5 Pb-free Symbol ...........................................................5 nd Second (2 ) Level Interconnect Component Label ...............................6 Size ...................................................................7 Color ...................................................................7
5 5.1 5.1.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4
Marking/Labeling Categories ......................... ......................7 PCB Base Material Categories ...............................................7 Halogen-free Base Material .................................................7 PCB Surface Finish Categories ..............................................7 Pb-containing ......................... ............................ ........7 Pb-free .......................... ........................... .............8 nd Second (2 ) Level Interconnect Categories .....................................8 Pb-containing ......................... ............................ ........8 Pb-free .......................... ........................... .............8 Conformal Coating Categories ...............................................9
6 6.1 6.2
Component Marking and Labeling ......................... .................9 Component Marking .......................................................9 Lowest Level Shipping Container Labeling ......................... .............9
7 PCB/Assembly Marking and Labeling........................... ............ 10 7.1 PCB Marking........ ........................... ......................... 10 7.1.1 PCB Shipping C ontainer Labeling ........................... ................ 10 7.2 Assembly Marking ................................... ..................... 10 7.2.1 Assembly Shipping Container Labeling ....................... ................ 10 7.3 Solder Category Marking Sequence .............................. ............ 10 7.4 Location .................................. ........................... ..10 7.5 Size........................ ........................... ................ 10 7.6 Color ..................................... ........................... ..10
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IPC/JEDEC Joint Standard J-STD-609B
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly Contents (cont'd) 7.7 7.8 7.9 7.10
Font ................... ............................ .................... 11 Method.......................... ........................... ............ 11 Marking Sequence .......................... .......................... ...11 Re-marking Changes in PCBA Materials ...................................... 11
8 8.1 8.2 8.3
Marking and/or Labeling of Pb-Containing Components, PCBs, and PCB Assemblies ..12
Marking and Labeling of Components ...................................... ..12 Marking and Labeli ng of PCBs ....... ........................... ............ 12 Marking and Labeling of PCB Assemblies ..................................... 12
9
Summary of Marking and Labeling Requirements R equirements........................... ..13
Annex A Example Alloys and Associated Material Codes ............................... 14 Annex B Material Code Flow Chart........................ Chart ........................ ......................... 15
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IPC/JEDEC Joint Standard J-STD-609B
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly
Foreword Directive 2011/65/EU supersedes 2002/95/EC of the European Parliament and of the Council on the restriction of the use of certain hazardous substances in electrical and electronic equipment, commonly referred to as the “RoHS 2 Directive”, and other legislation are driving the electronics industry towards the use of lead-free (Pb-free) solders and components with Pb-free 2 nd level interconnect terminal finishes and materials. There are different Pb-free solders being used for the various soldering operations in electronics. Each of these solders may require different processing temperatures for assembly, rework, and repair. Some means of communicating the identity of the Pb-free or Pb-containing solder must be provided so that those performing assembly, rework and repair are aware of the temperature capabilities and limitations of these solders, and are able to distinguish between Pb-free and Pb-containing solders. Marking of components and/or labeling their shipping containers are needed to identify and distinguish Pb-containing and Pb-free 2 nd level interconnect terminal finishes and materials. Labeling electronic assemblies using Pb-free solder materials will facilitate end-of-life recycling of electronic equipment. This standard sets forth minimum requirements and includes options for the provision of additional information. This paradigm shift to Pb-free electronics has created a need for identification of traditional Pb-containing coatings, finishes and solders. This standard can be utilized to identify the presence of Pb for those markets as described in Section 5 (Marking/Labeling Categories) and Section 8 (Marking and/or Labeling of Pb-Containing Components, PCBs, and PCB Assemblies). This standard supersedes JESD97 and IPC-1066.
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IPC/JEDEC Joint Standard J-STD-609B
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IPC/JEDEC Joint Standard J-STD-609B Page 1
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly (From JEDEC Board Ballot JCB-15-55, formulated under the cognizance of the JC-14.4 Subcommittee on Quality Processes and Methods.)
1
Scope
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes. This standard describes the marking of components and the labeling of their shipping containers to identify their 2 nd level terminal finish or material, and applies to components that are intended to be attached to boards or assemblies with solder or mechanical clamping or are press fit. This standard also applies to 2 nd level terminal materials for bumped die that are used for direct board attach. This standard applies to boards/assemblies, to identify the type of Pb-free or Pb-containing solder used. This standard documents a method for identifying board surface finishes and Printed Circuit Board (PCB) resin systems. This standard applies to PCB base materials and for marking the type of conformal coating utilized on Printed Circuit Board Assemblies (PCBAs). Material and their containers previously marked or labeled according to JESD 97, IPC-1066, or previous versions of this standard need not be remarked unless agreed upon by the supplier and customer. Labeling of exterior surfaces of finished articles, such as computers, printers, servers, and the like, is outside the scope of this standard. However internal PCBs and PCBAs are covered by this standard. Labeling of retail packages containing electronic products is also outside the scope of this standard. Markings under this standard do not denote EU RoHS compliance, or any other regional substance restriction legislation addressing lead content. 1.1
Purpose
This standard provides a marking and labeling system that aids in assembly, rework, repair and recycling and provides for the identification of: (1) those assemblies that are assembled with Pb-containing or Pb-free solder; (2) components that have Pb-containing or Pb-free 2 nd level interconnect terminal finishes and materials; (3) the maximum component temperature temperatur e not to be exceeded during assembly or rework processing; (4) the base materials used in the PCB construction, including those PCBs that use halogenfree resin; (5) the surface finish of PCBs; and (6) the conformal coating on PCBAs.
IPC/JEDEC Joint Standard J-STD-609B Page 2
2
Reference Documents
2.1
IPC
URL: www.ipc.org IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-CC-830 Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies (Conformal Coating) IPC-4101 Specification for Base Materials for Rigid and Multilayer Printed Boards 2.1.1
Additional Reference Reference Materials Not Found in This Document
ANSI URL: www.ansi.org/ ANSI 17-1981 Character Set for Optical Character Recognit ion (OCR-A) (OCR- A) GEIA SAE-GEIA-STD-0005-1 Performance Standards for Aerospace and High Performance Electronic Systems Containing Lead-free Solder SAE-GEIA-STD-0005-2 Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems SAE-GEIA-STD-0005-3 Performance Testing for Aerospace Aerospace High Performance Electronic Interconnects Containing Pb-free Solder and Finishes European Standards NBN EN 50581 (2012) Cenelec EU RoHS Recast CE Mark Technical Document Standard 2.2
JEDEC
URL: www.jedec.org JESD88 JEDEC Dictionary of Terms of Terms for Solid State Technology 2.3
IEC
URL: www.iec.ch IEC 61249-2-21 Materials for printed boards boards and other interconnecting structures - Part 2-21: Reinforced base materials, clad and unclad - Non-halogenated epoxide woven E-glass reinforced laminated sheets of defined flammability (vertical burning test), copper-clad. 2.4
European Parliament
URL: http://ec.europa.eu/environment/waste/weee/index_en.htm Directive 2011/65/EU of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment.
IPC/JEDEC Joint Standard J-STD-609B Page 3
3
Terms and Definitions
Other than those terms listed below, the definitions of terms used in this standard are in accordance with IPC-T-50 and/or JESD88. 3.1
2D code label (matrix)
A label that contains data in two dim ensions as either stack or matrix types. 3.2
2Li (or 2LI)
Abbreviation for 2 nd level interconnect. 3.3
Second (2 nd) level interconnect
The connection made by attaching a component to a printed circuit board. See Figure 3-1. This connection is external to the component, not internal.
Figure 3-1 Examples of materials that comprise comprise the 2 nd Level Interconnect 3.4
Second (2 nd) level interconnect component label
A label placed on boxes and bags that contain components with either Pb-containing or Pbfree terminal materials/ finishes. The label includes the material category and maximum component temperature (see 3.11 and 3.12). See Figure 4-3 for label formats for components with Pb-containing finishes/materials and Figure 4-4 and Figure 4-5 for components with Pbfree finishes/materials. 3.5
Second (2 nd) level interconnect terminal finish or material
The material at the component 2 nd level termination referred to in Figure 3-1. Depending on the component type this material could refer to the terminal finish or ball material. 3.6
Base materials
The laminates and/or the prepregs used to fabricate the printed circuit board. NOTE A prepreg is a sheet of material that has been been impregnated with a resin cured to an intermediate stage, i.e., B-staged resin. (Ref: IPC-T-50)
3.7
Component
An individual part such as a connector, capacitor, integrated circuit, socket, multichip module, or hybrid circuit, etc.
IPC/JEDEC Joint Standard J-STD-609B Page 4
3
Terms and Definitions (cont’d)
3.8
Halogen-free board
Printed board resins plus reinforcement matrix that contain maximum total halogens of 1500 ppm with less than 900 ppm bromine and less than 900 ppm chlorine (per IEC 61249-2-21). 3.9
intct (or INTCT)
Alternative abbreviations for the word “interconnect .” 3.10
Linear bar code label
A label that gives information in a code consisti ng of parallel bars and spaces. spaces . 3.11
Material category
Solder paste, lead/terminal finish, or terminal material/alloy of the solder balls used to make the 2nd level interconnect. 3.12
Maximum component temperature
The temperature that a component should not exceed during assembly as measured on the top of the component body. 3.13
Pb-free; lead free
Having a maximum Pb concentration value of of 0.1% by weight in PCB surface finishes, component terminal finishes (terminal finish, bump or ball material) and attachment solders. NOTE Component and end-product suppliers may desire to clarify this important distinction (between 0% and 0.1% Pb) with their customers.
3.14
Pb-free symbol
A symbol that can be used in place of the phrase “Pb -free” or “lead“lead -free.” See Figure 4-2. 4 -2.
IPC/JEDEC Joint Standard J-STD-609B Page 5
4
Symbols, Labels, and Marks
4.1
Material Category Symbol
This symbol (see Figure 4-1) is used to identify a terminal finish or material listed in 5.3.
NOTE 1 If the Materials Category is used without a circle, ellipse, parentheses parentheses or underline, underline, it must be be made clear that the marking defines the category [e.g. “Category = e2”, or “Solder = e2” ] NOTE 2 The letter “e” would be replaced with a “b” for identifying surface finish material listed in 5.2 for PCBs.
Figure 4-1 — Example of mark indicating material category 2 and the optional circle, ellipse, underline or parentheses 4.1.1
Size and Location
The size and location are discretionary, but shall be shall be legible to corrected, unmagnified vision. 4.1.2
Color
The color for the ‘e’ a nd category number should be selected to provide sufficient contrast to be legible to corrected, unmagnified vision. The color red should be avoided as red suggests a personal hazard. 4.1.3
Font
The font style should be “Arial”, “OCR - A” A” or equivalent. 4.2
Pb-free Symbol
This symbol (see Figure 4-2) can be used in addition to, or instead of, the phrase “Pb-free. “ Pb-free.””
Figure 4-2 — Pb-free Symbol
IPC/JEDEC Joint Standard J-STD-609B Page 6
4.3
Second (2 nd) Level Interconnect Component Label
This label (see Figure 4-3, Figure 4-4, and Figure 4-5) is used to indicate the 2 nd level interconnect terminal finish or material category (Clause 5) and maximum component temperature. The Pb-free symbol (See 4.2) may be appended after the terms “2nd Level Interconnect” Interconnect ” as indicated in Figure 4-5. This use of the Pb-free symbol applies only to the 2 nd level interconnect and should not be interpreted as an indication that any other part of the component is Pb-free. This label, if used, is placed/printed on the lowest level shipping container and any “ESD”, ”Dry pack” or other ot her bag/box, excluding tubes, trays, reels or other carriers, within the lowest level shipping container.
Figure 4-3 — Example of 2 nd Level Interconnect Component Label indicating a Pb-containing material
Figure 4-4 — Example of 2 nd Level Interconnect Component Label indicating a Pb-free e2 material with a maximum component temperature of 260ºC
Figure 4-5 — Example of 2 nd Level Interconnect Component Label utilizing the Pb-free symbol indicating both Pb-free material with category and maximum component temperature indicated on adjacent label
IPC/JEDEC Joint Standard J-STD-609B Page 7
4.3
Second (2 nd) Level Interconnect Component Label (cont’d)
4.3.1
Size
It is recommended that the label be a minimum of 75 mm by 50 mm. 4.3.2
Color
The label shall be shall be black letters/symbols on a white or contrasting background.
5
Marking/Labeling Categories
These categories are for the technical purposes of this standard and are not to be used for determining regulatory compliance. 5.1
PCB Base Material Categories
The PCB base materials may be identified by using the classification system found in IPC4101, where a unique Specification Sheet (“slash -sheet”) number identifies a specific grade of material. Some of the common base materials expected to be used on PCBs are given. However, other grades of base materials are possible. These base materials have an epoxy resin system with woven-glass reinforcement, plus distinguishing properties. a) / 92: Phosphorous flame retardant; Tg 110 °C to 150 °C b) / 95: Aluminum Hydroxide flame retardant; Tg 150 °C to 200 °C c)
/ 99: Bromine flame retardant; contains inorganic fillers; Tg 150 °C min.
d) / 126: Bromine flame retardant; contains contains inorganic fillers; Tg 170 170 °C min.
For PCBs made with more than one grade of materials, mark or label with the slash-sheet number of the material with the lowest temperature rating. 5.1.1
Halogen-free Base Material
If the base materials used in making the bare printed board are halogen-free, the label/marking 'HF' shall be noted on the bare printed circuit board. If no 'HF' is present, a halogen-containing base resin and reinforcement matrix are assumed. This marking applies only to the PCB base material and is not to be interpreted as an indication of a halogen-free (HF) assembly. 5.2
PCB Surface Finish Categories
The following categories describe the predominant surface finish on the bare board (prior to assembly). 5.2.1
Pb-containing
b0 – b0 – contains contains Pb, traditional tin-lead (SnPb), hot air solder level (HASL) or solder reflow.
IPC/JEDEC Joint Standard J-STD-609B Page 8
5.2
PCB Surface Finish Categories (cont’d)
5.2.2
Pb-free
b1 b2 b3 b4 b5
Pb-free HASL [tin (Sn) alloys with no bismuth (Bi) nor zinc (Zn)] immersion silver (Ag) tin (Sn) (electrolytic or immersion) gold (Au) (immersion or or electrolytic), electroless nickel immersion gold (ENIG), nickel gold (NiAu), or electroless nickel electroless palladium immersion gold (ENEPIG) screened carbon (carbon ink)
b6 b7 b8
organic solderability preservative (OSP) Unassigned Unassigned
b9
Unassigned
5.3
Second (2 nd) Level Interconnect Categories
The following categories describe the 2 nd level interconnect (see Figure 3-1) terminal finish (terminal finish, bump or ball material) of components or the solder paste/solder used in board assembly. 5.3.1
Pb-containing
e0 – e0 – contains contains intentionally added Pb 1 (need to change footnote # to 1) 5.3.2
Pb-free
Category e8 was added in this revision and shall be shall be applied to the labeling and marking of all new items. Previously marked items need not be remarked to comply with this standard. Items previously labeled or marked as e1 or e2 may now be described by the definitions of categories e1, e2, or e8 depending on silver content. e1 e2 e3 e4 e5 e6 e7 e8
e9
tin-silver-copper (SnAgCu) with silver content greater than 1.5% and no other intentionally added elements tin (Sn) alloys with no bismuth (Bi) nor zinc (Zn), excluding tin-silver-copper tin -silver-copper (SnAgCu) alloys in e1 and e8 tin (Sn) precious metal (e.g., silver (Ag), gold (Au), nickelnickel-palladium palladium (NiPd), nickel-palladium-gold (NiPdAu) (no tin (Sn)) tin-zinc (SnZn), tin-zinc-other (SnZnX) (all other alloys containing tin (Sn) and zinc (Zn) and not containing bismuth (Bi)) contains bismuth (Bi) low temperature solder ( ≤ 150 ºC) containing indium (In) [no bismuth (Bi)] tin-silver-copper (SnAgCu) with silver content less than or equal to 1.5%, with or without without intentionally added alloying elements. This category does not include any alloys described by e1 and e2 or containing bismuth or zinc in any quantity. symbol - unassigned.
See Annex A and Annex B for examples of Pb-free e-code applications and e-code selection. 1
nd
For Pb-containing 2 level interconnect terminal finishes and materials, the Pb content for e0 is typically greater than or equal to 3 percent by weight. For Pb-containing solder, solder paste, and wave solder alloy, the Pb content is typically greater than 3 percent by weight and usually is 37 percent by weight.
IPC/JEDEC Joint Standard J-STD-609B Page 9
5.4
Conformal Coating Categories
The following categories (per IPC-CC-830) shall describe the conformal coating, if used. ER – ER – Epoxy Epoxy Resin UR – UR – Urethane Urethane Resin AR – AR – Acrylic Acrylic Resin SR – SR – Silicone Silicone Resin XY – XY – Paraxylylene Paraxylylene
6
Component Marking and Labeling
6.1
Component Marking
If space permits, the individual component shall shall be marked (per 5.3) on its topside with the Material Category designation enclosed within a circle, ellipse, underlined, or in parentheses (See 4.1). See Figure 6-1 for an example. If the 2 nd level interconnect termination finish or material is removed and replaced on a component, the original ‘e’ code marking on that physical component shall be shall be obliterated and the component shall be remarked with the applicable ‘e’ code in accordance with this standard.
Figure 6-1 — Example of Component Marking 6.2
Lowest Level Shipping Container Labeling
The Material Category and the maximum component body temperature shall be shall be indicated on nd the lowest level shipping container utilizing the 2 level interconnect component label (See Figure 4-4). 4-4). The use of the 2 nd level interconnect component label is not required if the following information is included in human readable form on the bar code (linear or 2D) label or other nearby label: a) the words “2 nd level interconnect” or equivalent abbreviation b) the appropriate materials category from 5.3, and c) the maximum component body temperature. The 2nd level interconnect component label applies only to components.
IPC/JEDEC Joint Standard J-STD-609B Page 10
7
PCB/Assembly Marking and Labeling
7.1
PCB Marking
Any printed circuit board surface finish with Pb >0.1% shall be shall be marked with the Pb category b0 (see 5.2). Space permitting, the printed circuit board finish may be marked with the material categories defined in 5.2. In addition, the base PCB material may also be marked with the material categories defined in 5.1. If space permits, the IPC base material specification number may be added before the slash sheet number if the specification is other than IPC4101. If specified by the purchaser, the PCB fabricator may be required to mark the PCB with the applicable category for solders (see 5.3) and/or conformal coating (see 5.4) to be used by the assembler. 7.1.1
PCB Shipping Container Labeling
The label on the lowest level PCB shipping container shall shall contain the information that is applicable to the bare board marking. 7.2
Assembly Marking
The solder paste/solder used shall shall be identified on an assembly, as defined in 5.3. If used, the conformal coating used shall shall be identified on an assembly, per 5.4. If the PCB was previously marked with the applicable category for solders (see 5.3) and/or conformal coating (see 5.4) and the sequence written does not match the materials used during assembly, the PCBA shall be shall be remarked in accordance with 7.10. 7.2.1
Assembly Shipping Container Labeling
The label on the lowest assembly level shipping container shall shall contain the information applicable to the assembly marking. 7.3
Solder Category Marking Sequence
If two or more solder alloy categories are used the category of the solders used shall be shown in the following sequence: Reflow, wave and other. For repair materials, refer to 7.10. 7.4
Location
The preferred location for marking the material categories on the board/assembly is on PCB layer 1 (topside) at the lower right-hand segment or next to the part/serial number on the board, or next to the company logo. The marking sequence shall shall be clearly identifiable and separate from other board markings. For instance, the marking sequence may be entirely within brackets or parentheses. See example in Figure 7-1. Alternative locations may be specified in procurement documentation. 7.5
Size
The size of the mark is optional but shall be shall be legible to corrected, unmagnified vision. 7.6
Color
The color for the ‘e’ and category number shall be shall be selected to provide sufficient contrast to be legible to corrected, unmagnified vision.
IPC/JEDEC Joint Standard J-STD-609B Page 11
7.7
Font
The font style should be “Arial ,” “OCR“OCR- A” A” or equivalent. 7.8
Method
The methods for marking of the board (e.g., screen print, etch, laser, label, modification of existing bar code, etc.) are optional but shall be shall be legible to corrected, unmagnified vision. 7.9
Marking Sequence
The sequence of marking, as required, shall be shall be as follows: a) base material slash sheet number (see 5.1) b) halogen-free (see 5.1.1) c)
PCB surface finish (see 5.2)
d) reflow, wave and other solders (see 5.3) e) conformal coating (if applicable, applicable, see 5.4)
Figure 7-1 shows an example of board/assembly markings. Examples: Multifunctional epoxy, halogen-free FR-4.1 laminate PCB with immersion silver (Ag) surface finish; assembly used tin-silver-copper (SnAgCu) solder for reflow and a tin (Sn) alloy with no bismuth (Bi) or zinc (Zn) excluding SnAgCu for wave attachment; no conformal coating. /95 HF b2 e1 e2
or /95-HF-b2-e1-e2
or /95/HF/b2/e1/e2
Halogen containing epoxy FR-4 laminate PCB with Pb-containing surface finish; assembled with Pb-containing solder; epoxy conformal coating. /99 b0 e0 ER
or /99-b0-e0-ER
or /99/b0/e0/ER
Figure 7-1 — Example of Board/Assembly Markings 7.10
Re-marking Changes in PCBA Materials
If changes, rework, or repair to assemblies are made with a material finish category code different than marked, then the marking sequence in 7.3 shall be shall be appended with the material code (See 7.3) for the rework or repair solder and/or conformal coating used.
IPC/JEDEC Joint Standard J-STD-609B Page 12
8
Marking and/or Labeling of Pb-Containing Components, PCBs, and PCB Assemblies
The use of any markings, labels, or symbols that contain the phrase “Pb-free” Pb-free” or the Pb-free symbol shown in Figure 4-2 for this section is prohibited. 8.1
Marking and Labeling of Components
Suppliers whose customers require labeling and marking to indicate Pb content in 2 nd level interconnect finishes and materials shall utilize shall utilize the Material Category code established in 5.3 nd (e0). The alternate 2 level interconnect component label as shown in Figure 4-3 shall be used unless the following information is included on the bar code (2D or linear) or other nearby label, in human readable form. 2 a) the words “2
nd
level interconnect” or equivalent abbreviation
b) the appropriate materials category category from 5.3, and c)
the maximum component body temperature. nd
d) The 2 level interconnect component label applies only to components.
8.2
Marking and Labeling of PCBs
Suppliers whose customers require labeling and marking of PCBs to indicate Pb content in PCB surface finishes shall shall utilize the Material Category code(s) as established in 5.2 (b0). Solders to be used in assembly may be marked with category code (e0) on the PCB if specified by purchaser. 8.3
Marking and Labeling of PCB Assemblies
Suppliers whose customers require labeling and marking of the PCB assembly to indicate Pb content in assembly solders shall utilize shall utilize the Material Category code e0 as established in 5.3.
2
nd
If the required information is included on another label, the use of the 2 level interconnect label becomes optional.
IPC/JEDEC Joint Standard J-STD-609B Page 13
9
Summary of Marking and Labeling Requirements
Table 9-1 summarizes the marking and labeling requirements detailed previously in this standard. Table 9-1 — Marking and Labeling Summary Item
Preferred Location
Marking or Labeling Content Requirements Required
Optional
Component Marking (Clause 6)
Component body, topside
- Material category for component terminal finish (terminal finish, bump or ball material) (5.3)
- Maximum component body temperature (3.12) -
Component Container Label (Clause 6)
Lowest level shipping container AND any “ESD”, “Dry Pack” or other bag or box within the shipping container
- Material category for component terminal finish (terminal finish, bump or ball material) (5.3) - Maximum component body temperature (3.12)
- Pb-free symbol or the phrase ‘Pb‘ Pbfree’ (4.2) nd - 2 Level Interconnect Component Label (4.3)
PCB Marking (7.1)
Topside, lower right-hand corner; or next to part/serial number or company logo
- PCB surface finish containing lead (Pb) (5.2) - Halogen-free mark [HF] if applicable (5.1.1) - Solders and conformal coating to be used by assembler if specified by purchaser
- IPC 4101 slashsheet number (5.1) - Pb-free PCB surface finish - Alternative IPC specification number if other than IPC4101
PCB Container Label (7.1.1)
Lowest level container holding PCBs
- Mark or label with the information applicable to the PCB
- Halogen-free mark [HF] if applicable (5.1.1)
PCBA Marking (7.2)
Topside, lower right-hand corner; or next to part/serial number, or company logo
- Mark with material category for assembly solder type(s) used (5.3) in the order of application (7.3) - Conformal Coating, if any (5.4)
PCBA Container Label (7.2.1)
Lowest level container holding PCBAs
Mark or label with the information applicable to the PCBA
Comments Space permitting
Sequence: Space permitting IPC spec. number, slashsheet no, [HF], PCB finish, solders, [conformal coating] (7.9)
Pb-free symbol marking or label cannot be used on PCBA if any PCB surface finish, solder or component terminal finish(terminal finish, bump or ball material) is not Pb-free (i.e.,<0.1% Pb, per 3.13)
IPC/JEDEC Joint Standard J-STD-609B Page 14
Annex A (informative) Example Alloys and Associated Material Codes Alloy Composition
e-code
Sn-2.0Ag-0.5Cu (SAC205)
e1
Sn-3.0Ag-0.5Cu (SAC305)
e1
Sn-4.0Ag-0.5Cu (SAC405)
e1
Sn-3.8Ag-0.9Cu (SAC387)
e1
Sn-3.5Ag
e2
Sn-3.7Ag
e2
Sn-4.0Ag
e2
Sn2Ag0.5Cu+0.05Ni
e2
SAC 305+0.05Ni+0.5In
e2
Sn-2.5Ag-0.5Cu+0.5Co
e2
Sn-3.5Ag + 0.05-0.25La
e2
Sn-0.7Cu
e2
Sn-3.0Ag-0.5Cu + 0.019Ce
e2
Sn-2.5Ag-0.8Cu-0.5Sb
e2
Sn-0.7Cu-0.05Ni
e2
Sn-0.7Cu-0.05Ni + Ge (SN100C)
e2
Sn- 58Bi
e6
Sn- 57Bi-1.0Ag
e6
Sn-0.3Ag-0.7Cu+Bi (SACX)
e6
Sn-0.3Ag-0.7Cu+Bi+Ni+Cr (SACX)
e6
Sn-1.0Ag-0.5Cu + 0.02Ti
e8
Sn-1.0Ag-0.7Cu+0.1Ge
e8
Sn-1.2Ag-0.5Cu+0.05Ni (LF35)
e8
Sn-1.0Ag-0.5Cu (SAC105)
e8
Sn-1.0Ag-0.1Cu+0.02Ni+0.05In
e8
IPC/JEDEC Joint Standard J-STD-609B Page 15
Annex B Material Code Flow Chart
NOTE Additional markings beyond those listed above will be required per Section 7, clause 7.1 and and Section 8, clause 8.1
IPC/JEDEC Joint Standard J-STD-609B Page 16
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JEDEC J-STD-609B
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